1. Field
One or more embodiments of the following description relate to a bus arbitration apparatus and method, and more particularly, to a bus arbitration apparatus and method based on characteristics of masters.
2. Description of the Related Art
Recently, as various types of application programs are implemented in a single system, the number of masters forming a system is increasing, and types and characteristics of masters are becoming diverse. Accordingly, a conventional bus arbitration method has been developed by focusing on a best performance shown by each of various masters in a system.
However, to improve overall system performance, performance of each master needs to be efficiently adjusted.
For example, assuming that four processors and a single shared memory are connected to a single bus system, when a request of a single processor transmitted to a bus is processed preferentially, 100% performance of the processor may be achieved, however, the other three processors may not achieve 100% performance, due to the influence of the preferentially processed processor. In this example, overall system performance may be matched to the three processors, instead of the processor achieving 100% performance. Accordingly, such a bus arbitration scheme may cause an efficiency problem.